Analysis of multi-core automotive chip architectures combining high-throughput application cores, deep learning accelerators, and lockstep safety microcontrollers.
Split-Lock technology allows CPU clusters to operate in two distinct modes: Split mode for maximum multithreaded compute throughput (running perception and infotainment), or Lock mode where pairs of cores execute instructions in lockstep for redundant ASIL-D safety verification.
To prevent non-safety operating systems from corrupting critical memory regions, ARM System MMUs (SMMUv3) enforce two-stage address translation on all bus master transactions. Direct Memory Access (DMA) requests from GPUs or network controllers cannot access memory belonging to ASIL-D control partitions.